Software/Hardware Design and Implementation of JPEG CODEC on FPGA

Image compression is an important topic in commercial, industrial,and academic applications. In the first part of this research: a Modified JPEG (ModJPEG) by using Matlab7.6 program is proposed,the modification is focused on decreasing the processing time required for execution while increasing both compression ratio and PSNR. The proposed algorithm uses the inter pixel redundancy as a factor for decreasing the number of operations required to compress and decompress images. The simulation results show that the ModJPEG algorithm can process a (256x 256) color image in a reduced processing time (more than 40%) compared to the conventional algorithm and by more resilience with higher compression ratio. In the second part: this thesis presents the design and performance measurement of the hardware JPEG CODEC (compressors and decompressor). The designed architecture is modeled using VHDL language and implemented on Spartan-3E FPGA chip through ISE10.1 program as a target technique to encodes and decodes colored as well gray image formats. The design exploits the pipeline architecture for high throughput.