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Routing Congestion in VLSI Circuits
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This book provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are equipped with the knowledge to prudently choose an approach that is appropriate to their design goals.This work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step.The subjects covered in this book include: a motivation that explains why the problem is important and how it will trend, definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
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