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Covering all three levels of parallelism, this book presents techniques that address performance issues in the programming of HPC applications. Drawing on their experience with chips from AMD and systems, interconnects, and software from Cray Inc., the authors explore the problems that create bottlenecks in attaining good performance. After discussing architectural and software challenges, they outline a strategy for porting and optimizing an existing application to a large MPP system. They also introduce the use of GPGPUs for carrying out HPC computations.