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Heterogeneous Mulit-pipeline ASIP
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Embedded systems are becoming ubiquitous, primarily due tothe fast evolution of digital electronic devices. The design ofmodern embedded systems, requires systems to exhibit, highperformance and reliability, yet have short design time and lowcost. Application Specific Instruction set processors (ASIPs) arewidely used in embedded system since they are economical to use,flexible, and reusable (thus saves design time). During the lastdecade research work on ASIPs have been carried out in mainly forsingle pipelined processors. Improving performance in processors ispossible by exploring the available parallelism in the program.Designing of multiple parallel execution paths for parallelexecution of the processor naturally incurs additional cost. Themethodology presented in this book has addressed the problem ofimproving performance in ASIPs, at minimal additional cost. Thedevised methodology explores the available parallelism of anapplication to generate a multi-pipeline heterogeneous ASIP. Theprocessor design is application specific, no pre-defined IPs areused in the design.
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