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Device Performance and Reliability in SOI MOSFET
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SOI MOSFET is one of the promising options for the future VLSI market due to its low power/high speed character and simplified technology with increased packing density. Yet some problems in device physics must be fully understood before SOI is implemented in industry. In this thesis, optimized technology directions to balance the tradeoff between Performance & Reliability in SOI MOSFET are suggested. 1. Extensive study on the opposite-channel-based injection (OCBI) by manipulating these two gates is carried out by copious PISCES simulations. 2. the channel coupling effect was extensively carried out; both on electric field and impact ionization by numerical simulation. 3. the width effect of floating body effect was analyzed by a two-dimensional simulation which mimics its three dimensional features. 4. a new FD SOI MOSFET structure is proposed, which holds the drawbacks of low channel mobility in the inversion mode and poor latch-up voltage in the accumulation mode. 5. the compatibility of LDD technology to SOI was studied.
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