Nu se pretează? Nu contează! La noi puteți returna bunurile în 30 de zile
Cu un voucher cadou nu veți da greș. În schimbul voucherului, destinatarul își poate alege orice din oferta noastră.
30 de zile pentru retur bunuri
This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.